Method of forming multiple gate insulators on a strained semiconductor heterostructure

ABSTRACT

A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.

[0001] The present application claims priority to U.S. ProvisionalPatent Application Ser. No. 60/296,617 filed Jun. 7, 2001.

BACKGROUND OF THE INVENTION

[0002] The present invention generally relates to the fabrication ofsemiconductor devices from substrates, and relates in particular to theuse of strained silicon (Si) heterostructure substrates in formingdevices such as transistors for example for high-performance CMOSintegrated circuit products.

[0003] As microelectronic devices require faster operating speeds andincreased computing power, the need exists for transistor circuits toprovide a greater complexity of transistors in a smaller amount ofcircuit real estate. Such microelectronic devices include, for example,microprocessors, ASICs, embedded controllers, and FPGAs. Eachmicroelectronic device consists of millions of transistors, such asmetal oxide semiconductor field-effect transistors (MOSFETs), that aredesigned to provide control over both the directional flow of electronsand the speed at which the electrons move through the circuits.

[0004] MOSFETs are conventionally fabricated on Si substrates, which arethe basic starting substrates on which semiconductor circuits are built.In order to create a MOSFET device on a Si substrate, a very thin layerof insulator is thermally grown or deposited on the Si substratefollowed by a polysilicon gate electrode definition to create a MOSFETdevice. Typically this insulator is SiO₂, or SiO₂ with a significantfraction of nitrogen, and so the insulator is typically referred to asthe gate oxide. The thickness of the gate oxide can determine thethreshold voltage that must be applied to the gate of a MOSFET to turnon the MOSFET device. The gate oxide thickness is used to define theMOSFET application. For example, high-performance microprocessors havecore logic devices with ultra-thin (e.g., 10-20 Å) gate oxides andinput/output devices with thicker gate oxides (e.g., 20-100 Å). As theoperational speed of electrical systems has increased, it has becomenecessary to have MOSFET devices with different gate oxide thicknesseson the same chip.

[0005] Conventional oxidation techniques for thermally growing oxidelayers on a Si substrate typically involve the consumption of asignificant portion of the Si substrate. For example, the amount of Sisubstrate that is lost in the oxidation process may be approximately onehalf of the thickness of the resulting thermally grown oxide layer.

[0006] Strained silicon heterostructures provide semiconductor deviceswith enhanced electron mobility and therefore speed. For example, seeU.S. Pat. No. 5,442,205. Strained silicon heterostructure substratestypically include a relatively thin (e.g., less than 250Å) strainedsilicon layer that may be used as the channel in a MOSFET device. If thelayer of strained silicon is grown too thick, misfit dislocation defectswill occur in the layer, compromising the yield (percentage offunctional devices) when MOSFET circuits are fabricated on thesubstrate. In particular, at a critical thickness, dislocations arefavored for strain relief of the epitaxial film over continuedaccumulation of strain energy. The critical thickness is a function ofthe lattice mismatch between the epitaxial film and substrate, as wellas the materials properties of both the epitaxial layer and thesubstrate. It is this critical thickness that may limit the usefulstrained silicon film thickness to less than, e.g., 250Å.

[0007] If too much of the strained silicon layer is consumed in theoxidation process, then the layer will be too thin to obtain thebenefits of the enhanced electron mobility. The minimum strained siliconfilm thickness required for significant mobility enhancement isapproximately 50Å. Conventional methods of forming multiple gate oxidesdo not work well on a strained Si substrate since the strained Si caplayer may be too thin to support the formation of both thick and thingate oxides. This is particularly the case since during a typical MOSFETfabrication process, there is much additional strained Si consumptiondue to various processing steps (cleans, thermal oxidations, anneals).

[0008] There is a need, therefore, for a method of forming strainedsilicon heterostructure substrates having a plurality of gate oxidethicknesses without sacrificing the enhance electron mobility of thesubstrates.

SUMMARY OF THE INVENTION

[0009] The invention provides a method for forming multiple gateinsulators on a strained semiconductor heterostructure as well as thedevices and circuits formed therefrom. In an embodiment, the methodincludes the steps of depositing a first insulator on the strainedsemiconductor heterostructure, removing at least a portion of the firstinsulator from the strained semiconductor heterostructure, and thermallygrowing or depositing a second insulator on the strained semiconductorheterostructure.

[0010] In an embodiment, the method of forming multiple gate insulatorson a strained silicon heterostructure includes the steps of depositing afirst insulator on the strained silicon heterostructure, applying afirst photoresist mask to at least a portion of the strained siliconheterostructure, removing at least a first portion of the firstinsulator from the strained silicon heterostructure, and thermallygrowing or depositing a second insulator on the strained semiconductorheterostructure. In further embodiments, the method further includes thesteps of applying a second photoresist mask to at least a portion of thestrained silicon heterostructure, removing at least a second portion ofthe second insulator from the strained silicon heterostructure, andthermally growing or depositing a third insulator on the strainedsilicon heterostructure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following description may be further understood withreference to the accompanying drawing in which

[0012] FIGS. 1-4 show diagrammatic views of a heterostructure substrateduring a method of providing a plurality of gate insulator thicknessesin accordance with an embodiment of the invention;

[0013]FIG. 5 shows a pair of FET devices formed on the substrate of FIG.4 where each device includes a different gate insulator thickness;

[0014]FIG. 6 shows the pair of FET devices of FIG. 5 coupled to acircuit;

[0015] FIGS. 7-11 show diagrammatic views of a heterostructure substrateduring a method of providing a plurality of gate insulator thicknessesin accordance with a further embodiment of the invention; and

[0016]FIG. 12 shows three FET devices formed on the substrate of FIG. 11where each device includes a different gate insulator thickness; and

[0017]FIG. 13 shows the three FET devices of FIG. 12 coupled to acircuit.

[0018] The drawings are shown for illustrative purposes and are not toscale.

DETAILED DESCRIPTION OF THE INVENTION

[0019] A strained Si substrate is generally formed by providing arelaxed SiGe layer on bulk Si through either eptitaxial deposition orwafer bonding, and then providing a Si layer on the relaxed SiGe layer.Because SiGe has a different lattice constant than Si, the Si layerbecomes “strained” and results in enhanced mobilities (and henceimproved device speeds) compared with bulk Si. The percentage of Ge inthe SiGe can have a dramatic effect on the characteristics of thestrained Si layer.

[0020] The invention provides a method of forming multiple gateinsulators on a substrate that includes strained semiconductor layers(e.g., strained silicon), where the thin and thick gate insulators areused for MOSFET transistors with different functionality. The resultingsubstrate allows the integration of MOSFETs with varying gate insulatorthicknesses, using strained semiconductor layers to increase speed andmobility of devices built on the substrate. An illustrative example ofsuch a substrate comprises a strained Si layer on a relaxed SiGe layer.FIG. 1 shows a cross-sectional view of a substrate 10, comprising a Silayer 12, a relaxed SiGe layer 14, and a strained Si surface layer 16.The strained Si layer 16 may be between 100Å and 300Å, and is preferablyless than 250Å in thickness. The substrate 10 forms the base structurefor the present invention. In developing this layered heterostructuresubstrate 10, epitaxial growth techniques and polishing techniques (forexample, chemical mechanical polishing) or wafer bonding techniques,which are known in the art, are applied. Methods of fabricating variousstrained silicon heterostructures are disclosed in U.S. patentapplication Ser. No. 09/906,551 filed Jul. 16, 2001 and U.S. patentapplication Ser. No. 09/928,126 filed Aug. 10, 2001, the disclosures ofwhich are hereby incorporated by reference.

[0021] As shown in FIG. 2, an insulator layer 18 (e.g., SiO₂) isdeposited on the strained Si layer 16, for example via Chemical VaporDeposition (CVD) or other methods to a thickness of e.g., 50 Å.Insulator layer 18 may include a thin (approx. 10 Å) thermal oxide layerat the interface with strained Si layer 16, which may be grown before orafter the deposition of insulator layer 18.

[0022] A photoresist masking layer 20 is then applied to a portion ofthe insulator layer 18 using photolithography techniques known in theart. The exposed portion of the insulator layer 18 is then removedusing, e.g., an HF acid or a CF₄/O₂ step, leaving photoresist maskinglayer 20 and insulator layer 18 as shown in FIG. 3. The photoresistmasking layer 20 is subsequently removed via wet etch (e.g., H₂SO₄+H₂O₂)or dry etch (e.g., oxygen plasma).

[0023] A second insulator layer 22 is then formed on the substrate by,e.g., thermal oxidation or deposition to a thickness of e.g., 10-20 Å asshown at part B in FIG. 4. When the second insulator layer 22 is formed,an oxide layer may be formed at the interface between the strainedsilicon layer 16 and the insulator layer 18 as shown at 26. Although theportion of the second insulator layer 26 in area designated part A maybe thinner then the portion of second insulator layer 22 in areadesignated part B, the combined thickness of the insulator layer 18 andthe insulator region 26 provide a composite insulator layer 24 as shownthat is thicker than the thickness of the insulator layer 22. Inparticular, the composite insulator layer 24 may be greater than e.g.,70Å in thickness and the insulator layer 22 may be 10-20 Å. Thesubstrate may be used, therefore, to form MOSFETs having multiple gateinsulator thicknesses.

[0024] As shown in FIG. 5, a pair of FET devices 30 and 32 may be formedon the parts A and B respectively of the structure of FIG. 4. The FETdevice 30 will include a gate insulator layer that is comprised of thecomposite insulator layer 24, and the FET device 32 will include a gateinsulator layer that is comprised of the insulator layer 22. The deviceseach include strained silicon channel 16 of a sufficient thickness thatthe mobility of the electrons is not compromised. The devices may beisolated from one another as disclosed in U.S. Provisional PatentApplication Ser. No. 60/296,976 filed Jun. 8, 2001 and U.S. patentapplication Ser. No. 10/___,___ filed Jun. 7, 2002, the disclosures ofwhich are both hereby incorporated by reference. The devices 30 and 32may be coupled to a circuit as shown in FIG. 6 in which the gate, sourceand drain of each FET are coupled to conductive paths of a circuit asgenerally shown at 34.

[0025] As shown in FIGS. 7-9 a heterostructure substrate 50 may again beformed of a silicon substrate 52, a relaxed layer 54 of SiGe and astrained silicon layer 56 in accordance with another embodiment of theinvention similar to the above disclosed embodiment shown in FIGS. 1-3.An insulator layer 58 of e.g., SiO₂ is then deposited on the strained Silayer 56 via CVD, as shown in FIG. 8, to a thickness of e.g., 30Å. Aphotoresist masking layer 60 is then applied to a portion of theinsulator layer 58 using photolithography techniques known in the art.The exposed portion of the insulator layer 58 is then removed using HFacid or a CF₄/O₂ step, leaving photoresist masking layer 60 andinsulator layer 58 as shown in FIG. 9. The photoresist masking layer 60is subsequently removed via wet etch (e.g., H₂SO₄+H₂O₂) or dry etch(e.g., oxygen plasma).

[0026] As shown in FIG. 10, a second insulator layer 62 is thendeposited via CVD on the substrate on both the insulator layer 58 andthe exposed portion of the strained silicon layer 56. The thickness ofthe second insulator layer 62 is, e.g., 30Å. A second photoresist mask68 is then applied to a portion of the substrate and the exposed portionof the insulator layer 62 is then removed using HF acid or a CF₄/O₂step, leaving photoresist masking layer 68 and insulator layers 62 and58 as shown in FIG. 11. The photoresist masking layer 68 is subsequentlyremoved via wet etch (e.g., H₂SO₄+H₂O₂) or dry etch (e.g., oxygenplasma).

[0027] A third insulator layer 70 is then formed on the substrate e.g.,by thermal oxidation or deposition to a thickness of e.g., 10-20Å asshown at part E in FIG. 12. When the third insulator layer 70 is formed,the insulator layer 66 may also be grown at the interface between thestrained silicon layer 56 and the insulator layer 58 as shown at part C,and an insulator layer 72 is formed at the interface with the strainedsilicon layer 56 as shown at part D. The combined thickness of theinsulator layer 58, the insulator region 66 and the second insulatorlayer 62 provide a composite insulator layer 74 as shown that is largerthan the thickness of the composite insulator layer 72 formed by theinsulator layer 62 and the insulator layer 72. Each of these compositeinsulator layers 74 and 72 is thicker than the insulator layer 70 asshown at part E in FIG. 12. The substrate may be used, therefore, toform MOSFETs having three different gate insulator thicknesses.

[0028] As shown in FIG. 13, three FET devices 80, 82 and 84 may beformed on the parts C, D and E respectively of the structure of FIG. 12.The FET device 80 will include a gate insulator layer that is comprisedof the composite insulator layer 74, the FET device 82 will include agate insulator layer that is comprised of the composite insulator layer72, and the FET device 84 will include a gate insulator layer that iscomprised of the insulator layer 70. The devices each include strainedsilicon channel 56 of a sufficient thickness that the mobility of theelectrons is not compromised. The devices maybe isolated from oneanother as disclosed in U.S. Provisional Patent Application Ser. No.60/296,976 filed Jun. 8, 2001 and U.S. patent application Ser. No.10/___,___ filed Jun. 7, 2002. The devices may be coupled to a circuitas shown in FIG. 13 in which the gate, source and drain of each FET arecoupled to conductive paths of a circuit as generally shown at 90. Thesubstrate may be used, therefore, to form MOSFETs having more than twomultiple gate insulator thicknesses.

[0029] The invention may also include one or more of the followingelements: relaxed SiGe layer 14 may comprise stained or relaxedsemiconductor layers other than SiGe, for example Ge or GaAs; strainedSi surface layer 16 may comprise strained SiGe or Ge layers; strained Silayer 16 may be above the critical thickness; and the substrate 10 maycomprise an insulating layer such as SiO₂, thus making the relaxed SiGelayer 14 optional. Those skilled in the art will appreciate thatnumerous modifications and variations may be made to the above disclosedembodiments without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of forming multiple gate insulators,said method comprising the steps of: providing a structure comprising astrained semiconductor layer; providing a plurality of insulator layersover said strained semiconductor layer, wherein each insulator layerpossesses a different thickness.
 2. The method as claimed in claim 1,wherein said step of providing a plurality of insulator layers involveschemical vapor deposition.
 3. The method as claimed in claim 1, whereinsaid step of providing a plurality of insulator layers involves thermaloxidation.
 4. The method as claimed in claim 3, wherein said step ofproviding a plurality of insulator layers further comprises: providing afirst insulator layer having a first thickness in a first region; andproviding a second insulator layer having a second thickness in a secondregion, wherein said first thickness is not equal to said secondthickness.
 5. The method as claimed in claim 4, wherein said methodfurther comprises removing at least a portion of said first insulatorlayer.
 6. The method as claimed in claim 4, wherein said method furthercomprises the step of removing at least a portion of said firstinsulator layer to form said second region.
 7. The method as claimed inclaim 4, wherein said first thickness is approximately 20Å toapproximately 100Å.
 8. The method as claimed in claim 4, wherein saidsecond thickness is approximately 10Å to approximately 20Å.
 9. Themethod as claimed in claim 4, wherein said method further comprisesproviding a third insulator having a third thickness in a third region,wherein said third thickness is not equal to said first thickness orsaid second thickness.
 10. The method as claimed in claim 1, whereinsaid method further includes the step of forming a plurality of devicesthat include said strained semiconductor layer, wherein each deviceincludes a gate insulator having a different thickness.
 11. Thestructure formed by the method of claim
 1. 12. The structure formed bythe method of claim
 10. 13. The method as claimed in claim 1, whereinthe strained semiconductor layer comprises Si.
 14. The method as claimedin claim 1, wherein the thickness of said strained semiconductor layeris less than approximately 300Å.
 15. The method as claimed in claim 1,wherein the plurality of insulator layers comprises silicon dioxide. 16.The method as claimed in claim 1, wherein said structure furthercomprises a relaxed semiconductor layer.
 17. The method as claimed inclaim 16, wherein said relaxed semiconductor layer comprises Ge or Si.18. A method of forming multiple gate insulators, said method comprisingthe steps of: providing a structure comprising a strained semiconductorlayer; providing a first insulator layer with a first thickness oversaid structure; removing said first insulator layer in a region; andproviding a second insulator layer with a second thickness in saidregion, wherein said second thickness is less than said first thickness.19. The method as claimed in claim 18, wherein said step of providing afirst insulator layer comprises chemical vapor deposition.
 20. Themethod as claimed in claim 18, wherein said step of providing a firstinsulator layer comprises thermal oxidation.
 21. The method as claimedin claim 18, wherein said step of providing a first insulator layercomprises chemical vapor deposition.
 22. The method as claimed in claim20, wherein said step of providing a second insulator layer furthercomprises chemical vapor deposition.
 23. The method as claimed in claim18, wherein said step of providing a second insulator layer comprisesthermal oxidation.
 24. The insulator structure formed by the method ofclaim
 18. 25. A structure comprising: a stained semiconductor layer; anda plurality of insulator layers disposed over said strainedsemiconductor layer, wherein each insulator layer possesses a differentthickness.
 26. The structure of claim 25, wherein the strainedsemiconductor layer comprises Si.
 27. The structure of claim 25 furthercomprising a relaxed semiconductor layer.
 28. The structure of claim 27,wherein said relaxed semiconductor layer comprises Si or Ge.
 29. Thestructure of claim 25, wherein the plurality of insulator layerscomprises silicon dioxide.
 30. The structure of claim 25, wherein theplurality of insulator layers comprises: a first insulator layer havinga first thickness in a first region; and a second insulator layer havinga second thickness in a second region, wherein said second thickness isless than said first thickness.
 31. The structure of claim 30, whereinsaid first thickness is approximately 20Å to approximately 100Å.
 32. Thestructure of claim 30, wherein said second thickness is approximately10Å to approximately 20Å.
 33. A semiconductor structure comprising: astrained semiconductor layer; and a plurality of devices comprising saidstrained semiconductor layer, wherein each device comprises an insulatorlayer of a different thickness.
 34. A circuit formed by theinterconnection of at least two devices of said plurality of devices ofclaim 33.